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GD32F310 数据表(PDF) 33 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD32F310
功能描述  Arm® Cortex®-M4 32-bit MCU
PDF  81 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD32F310 数据表(HTML) 33 Page - GigaDevice Semiconductor (Beijing) Inc.

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GD32F310xx Datasheet
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Functional description
3.1
Arm® Cortex®-M4 core
The Arm® Cortex®-M4 processor is a high performance embedded processor with DSP
instructions which allow efficient signal processing and complex algorithm execution. It brings
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital
signal control markets demand. The processor is highly configurable enabling a wide range
of implementations from those requiring memory protection and powerful trace technology to
cost sensitive devices requiring minimal area, while delivering outstanding computational
performance and an advanced system response to interrupts.
32-bit Arm® Cortex®-M4 processor core:
Up to 72 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M4 processor is based on the Armv7-M architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire Debug Port (SW-DP)
Trace Port Interface Unit (TPIU)
3.2
On-chip memory
Up to 64 Kbytes of Flash memory
 The region of the MCU executing instructions without waiting time is up to 64K bytes (in
case that Flash size equal to 16K, 32K or 64K, all memory is no waiting time). A long
delay when CPU fetches the instructions out of the range.
Up to 8 Kbytes of SRAM with hardware parity checking
The Arm® Cortex®-M4 processor is structured in Harvard architecture which can use separate
buses to fetch instructions and load/store data. 64 Kbytes of inner Flash at most, which
includes code Flash and data Flash is available for storing programs and data, and there is



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