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GD32F310 数据表(PDF) 62 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32F310 数据表(HTML) 62 Page - GigaDevice Semiconductor (Beijing) Inc. |
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62 / 81 page ![]() GD32F310xx Datasheet 61 4.17 I2S characteristics Table 4-36. I2S characteristics Symbol Parameter Conditions Min Typ Max Unit fCK(1) Clock frequency Master mode (data: 16 bits, Audio frequency = 96 kHz) 3.084 3.086 3.088 MHz Slave mode 0 — 10 tH(1) Clock high time — 162 — — ns tL(1) Clock low time 162 — — ns tV(WS) (2) WS valid time Master mode — 1.88 — ns tH(WS) (2) WS hold time Master mode — 2.5 — ns tSU(WS) (1) WS setup time Slave mode 0 — — ns tH(WS) (1) WS hold time Slave mode 2 — — ns Ducy(sck) (1) I2S slave input clock duty cycle Slave mode — 50 — % tSU(SD_MR) (1) Data input setup time Master mode 2 — — ns tSU(SD_SR) (1) Data input setup time Slave mode 0 — — ns tH(SD_MR) (1) Data input hold time Master receiver 0 — — ns tH(SD_SR) (1) Slave receiver 1 — — ns tV (SD_ST) (2) Data output valid time Slave transmitter (after enable edge) — 13.5 — ns tH (SD_ST)(2) Data output hold time Slave transmitter (after enable edge) — 13.8 — ns TV(SD_MT)(2) Data output valid time Master transmitter (after enable edge) — 7.55 — ns tH(SD_MT)(2) Data output hold time Master transmitter (after enable edge) — 8.33 — ns (1) Guaranteed by design, not tested in production (2) Based on characterization, not tested in production. |
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