GD32F310 datasheet(35/81 Pages) GIGADEVICE

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GD32F310xx Datasheet

the internal boot ROM memory (system memory). It is used to reprogram the Flash memory

by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15).

3.5

Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power

consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating

modes reduce the power consumption and allow the application to achieve the best balance

between the CPU operating time, speed and power consumption.



Sleep mode

In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and

any interrupt/event can wake up the system.



Deep-sleep mode

In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed

crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and

registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the

system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC

tamper and timestamp, LVD output and USART wakeup. When exiting the deep-sleep

mode, the IRC8M is selected as the system clock.



Standby mode

In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of

IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except

backup registers) are lost. There are four wakeup sources for the standby mode,

including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the

rising edge on WKUP pin.

3.6

Analog to digital converter (ADC)



12-bit SAR ADC's conversion rate is up to 2.86 MSPS



12-bit, 10-bit, 8-bit or 6-bit configurable resolution



Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit



Input voltage range: VSSA to VDDA (2.6 to 3.6 V)



Temperature sensor

One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19

multiplexed channels: 10 external channels, 1 channel for internal temperature sensor

(VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage

(VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling

scheme improves performance while off-loading the related computational burden from the

CPU. An analog watchdog block can be used to detect the channels, which are required to

remain within a specific threshold window. A configurable channel management block can be

used to perform conversions in single, continuous, scan or discontinuous mode to support

more advanced use.

GD32F310 数据表(PDF) 35 Page - GigaDevice Semiconductor (Beijing) Inc.

GD32F310 数据表(HTML) 35 Page - GigaDevice Semiconductor (Beijing) Inc.

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