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GD32F310 数据表(PDF) 64 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32F310 数据表(HTML) 64 Page - GigaDevice Semiconductor (Beijing) Inc. |
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64 / 81 page ![]() GD32F310xx Datasheet 63 4.18 USART characteristics Table 4-37 . USART characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency fPCLKx = 72 MHz — — 36 MHz tSCK(H) SCK clock high time fPCLKx = 72 MHz 13.8 — — ns tSCK(L) SCK clock low time fPCLKx = 72 MHz 13.8 — — ns (1) Guaranteed by design, not tested in production. 4.19 TIMER characteristics Table 4-38 . TIMER characteristics(1) Symbol Parameter Conditions Min Max Unit tres Timer resolution time — 1 — tTIMERxCLK fTIMERxCLK = 72 MHz 13.9 — ns fEXT Timer external clock frequency — 0 fTIMERxCLK/2 MHz fTIMERxCLK = 72 MHz 0 36 MHz RES Timer resolution — — 16 bit tCOUNTER 16-bit counter clock period when internal clock is selected — 1 65536 tTIMERxCLK fTIMERxCLK = 72 MHz 0.0139 910 μs tMAX_COUNT Maximum possible count — — 65536 × 65536 tTIMERxCLK fTIMERxCLK = 72 MHz — 59.6 s (1) Guaranteed by design, not tested in production. 4.20 WDGT characteristics Table 4-39. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) Prescaler divider PSC[2:0] bits Min timeout RLD[11:0] = 0x000 Max timeout RLD[11:0] = 0xFFF Unit 1/4 000 0.025 409.525 ms 1/8 001 0.025 819.025 1/16 010 0.025 1638.025 1/32 011 0.025 3276.025 1/64 100 0.025 6552.025 1/128 101 0.025 13104.025 1/256 110 or 111 0.025 26208.025 (1) Guaranteed by design, not tested in production. |
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