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ST52T301 数据表(PDF) 62 Page - STMicroelectronics |
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ST52T301 数据表(HTML) 62 Page - STMicroelectronics |
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62 / 100 page ![]() AND Logical AND Format: AND regi, regj Operation: regi <- regi AND regj Description: The instruction logically ANDs the contents of the Register File j-th register specified as source and the destination i-th register in the Register File, leaving the result in the desti- nation register. Flags: Z set if result is zero, cleared otherwise. S not affected. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 10011100 and the register 12 contains the value 01010101, then the instruction AND 4,12 10010001 0100|1100 causes the register 4 of the Register File to be loaded with the value 00010100. 62/99 ST52T301/E301 |
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