ST52T301 datasheet(30/100 Pages) STMICROELECTRONICS

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7. TIMER

ST52x301 offers one on-chip Timer peripheral.

TheTimer consists of an 8-bit counter with a 16-bit

programmable prescaler, thus giving a maximum

count o f 224, and control logic that allows

configuring the functionment and the type of

peripheral outputs. Figure 7.2 shows the Timer

block diagram and Figure 7.3 shows the internal

structure of the Timer.

The content of the 8-bit counter can be read/written

and is incremented on the Rising Edge of the 16-bit

prescaler output (PRESCOUT). Moreover, it can be

read under program control at any instant of the

counting phase and loaded in a location of the

between 0 and FFFFh setting the 4-th (TMLSB)

and 5-th (TMMSB) locations of the Configuration

Registers Bench.

7.1 Timer Functionment

The Timer requires three signals: TMRCLK, TRST

and TSTART (see Figure 7.3). Each of them can be

generated internally or externally, this possibility is

programmable by the user.

TMRCLK increments the counted value of the

Presc ale r. It can b e, by se tting C KSL of

REG_CONF6 register, the internal clock signal

(CLKM) or the signal provided on the pin TCLK.

TRST resets to zero the content of the 8 bit counter.

It is generated by the TRES or RESET external

signals or it is forced by TMRSTbit of REG_CONF6

TSTART starts/stops the Prescaler counting.It can

be given on the pin TCTRL or it is forced by TMST

bit of REG_CONF6 register.

The TSTART signal allows to work in two different

modes:

LEVEL (Time Counter): If the TSTART signal is

high the Timer starts the count. When the TSTART

is low the count is stopped and the current value is

stored in the TMR_OUT register of the Input

location of the Registers File by using the

instruction:

LDRI reg-j 4

EDGE(Period Counter): After the reset, when the

first edge of the TSTART signal appears, the Timer

starts the count, at the next TSTART the Timer is

stopped. In this way it is possible to measure the

period of an external signal.

The functionment modality is set by the TMEL

configuration bit of REG_CONF6 register.

The starting value of the Counter can be either a

value contained in the Register File or directly a

Fuzzy Output. If INPSL (REG_CONF7(3)) is set to

”1” then the value comes from one of the locations

of the Register File (LDRP 0, reg-i); on the

contrary it is generated by the Fuzzy Core. The

choice between the two possible fuzzy outputs is

set by the FZSL configuration bit of REG_CONF6

FZSL=0/1 means the starting value is the loaded

from the FUZZY_OUT_0/1.

Level

Edge

start

stop

start

stop

start

Reset

Clock

Counted

Value

Figure 7.1. Timer Functionalities

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ST52T301/E301

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