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ST52T301 数据表(PDF) 24 Page - STMicroelectronics |
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ST52T301 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 100 page  4.3 Interrupt Sources ST52x301manages interrupt signals generated by the internal peripherals (Timer, Triac/PWM Driver,Analog to Digital Converter and Serial Communication Port) or coming from the INT pin. Th e polar it y of t he Ext er n al I nt er rupt is programmed by the EXTI bit of the REG_CONF14 (see Table 4.1 and fig. 4.4). EXTI=0 means that INT_EXT is active on rising edge, otherwise it is active on falling edge. Each peripheral can be programmed in order to generate the associate interrupt;further detailsare described in the related chapter. 4.4 Interrupt Maskability The interrupts can be masked by configuring the REG_CONF14. The interrupt is enabled when the bit associated to the mask interrupt is ”1”. Viceversa, when the bit is ”0”, the interrupt is masked and is kept pendent. For example LDCF 14, 6 (CONF_REG14 =00000110) enables interrupts coming from the ADC (INT_ADC) and from the SCI (INT_SCI). 4.5 Interrupt Priority Six priority levels are available: level 5 has the lowest priority, level 0 has the highest priority. Level 5 is associated to the Main Program, levels 4 to 1 are programmable by means of the priority register called REG_CONF15 (see fig.4.5); whereas the higher level is related to the external interrupt (INT_EXT). Timer, Triac/PWM Driver, SCI and ADC are identified by a two bits Peripheral Code (see Table 4.2); in order to set the i-th priority level the user must write the peripheral label i in the related INTi priority level. Bit Name Value Description 0 MSKE 0 External Interrupt Masked 1 External Interrupt Not Masked 1 MSKAD 0 A/D Converter Interrupt Masked 1 A/D Converter Interrupt Not Masked 2 MSKSCI 0 SCI Interrupt Masked 1 SCI Interrupt Not Masked 3 MSKTM 0 TIMER Interrupt Masked 1 TIMER Interrupt Not Masked 4 MSKTC 0 TRIAC/ PWM Interrupt Masked 1 TRIAC/ PWM Interrupt Not Masked 5 not used - 6 not used - 7 EXTI 0 Active on Rising Edge 1 Active on Falling Edge Table 4.1. Configuration Register 14 Description Name Description Priority Peripheral Code Maskable EPROM Locations INT_EXT External Interrupt (INT) Ext Highest - yes 200-201 INT_ADC ADC Int Programmable 00 yes 192-193 INT_SCI SCI Int Programmable 01 yes 194-195 INT_TIMER TIMER Int Programmable 10 yes 196-197 INT_TRIAC TRIAC Int Programmable 11 yes 198-199 Table 4.2. Interrupts Description 24/99 ST52T301/E301 |
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