ST52T301 datasheet(23/100 Pages) STMICROELECTRONICS

23 / 100 page

4 INTERRUPTS

The Control Unit (CU) responds to peripheral

events and external events through its interrupt

channels.

When such an event occurs, if it is not masked and

according to a priority order, the current program

execution can be suspended to allow the CU to

execute a specific response routine.

Each interrupt is associated with an interrupt vector

that contains the memory address of the related

interrupt service routine. Each vector is located in

the Program Space (EPROM Memory) at a fixed

address (see Interrupt Vectors table fig. 4.2).

4.1 Interrupt Functionment

If, at the end of an arithmetic or logic instruction,

there are pending interrupts, the one with the

highest priority is passed. To pass an interrupt

means to store the arithmetic flags and the current

PC in the stack and execute the associated

Interrupt routine, whose address is located in one

of the EPROM memory location between address

192 and 201.

The Interruptroutine is performedas a normal code

checking, at the end of each instruction, if a higher

priority interrupt has to be passed. An Interrupt

request with the higher priority stops the lower

priority Interrupt. The Program Counter and the

arithmetic flags are stored in the stack.

With the instruction RETI (Return from Interrupt)

the arithmetic flags and Program Counter (PC) are

restored from the top of the stack.This stack, used

for the Interrupt priority, is a LIFO queue.

An Interrupt request cannot stop the processing of

the fuzzy rules but this is passed only after the

definitionof the fuzzy output or at the end of a logic

or arithmetic instruction.

4.2 Global Interrupt Request Enabling

When an Interrupt occurs, it generates a Global

Interrupt Pending (GIP), that can be hanged up by

software. After a GIP a Global Interrupt Request

(GIR) will be generate and Interrupt Service

Routine associated to the interrupt with higher

priority will start.

In order to avoid possible conflicts between

interrupt masking set in the main program or inside

macros, the GIP is hanged up through the User

Global Interrup Mask or the Macro Global Interrup

Mask (see fig.4.3).

UEGI/UDGI instruction switches on/off the User

Global Interrup Mask enabling/disablingthe GIR for

the main program.

MEGI/MDGI instructions set the Macro Global

Interrupt Mask in order to assure that the macro will

not be broken.

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE

ROUTINE

RETI

INSTRUCTION

INTERRUPT

Figure 4.1. Interrupt Flow

Interrupt Vectors

INT_TIMER

198

196

200

199

197

195

194

193

192

191

INT_SCI

INT_ADC

INT_TRIAC

INT_EXT

202

201

Figure 4.2. Interrupt Vectors Mapping

Global Interrupt

Pending

User Global

Interrupt Mask

Macro Global

Interrupt Mask

Global Interrupt

Request

Figure 4.3. Global Interrupt Request generation

23/99

ST52T301/E301

ST52T301 数据表(PDF) 23 Page - STMicroelectronics

ST52T301 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载