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ST52T301 数据表(PDF) 40 Page - STMicroelectronics |
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ST52T301 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 100 page  It means that each LDPR instruction deletesthe old value contained in the parallel port stack register and rewrite a newvalue on the same stack register. Only the last LDPR instruction is executed if the READY signal is maintained high during several LDRP instructions. Bit Name Value Description 0P8 - Digital Output Bit 1 ECKF 00 5 MHz 01 10 MHz 2 10 20 MHz 11 20 MHz 3 TXC 0 SCI End Transmission Interrupt Disabled 1 SCI End Transmission Interrupt Enabled 4 TDRE 0 SCI Transmission Data Register Empty Interrupt Disabled 1 SCI Transmission Data Register Empty Interrupt Enabled 5 BRK 0 SCI Break Error Interrupt Disabled 1 SCI Break Error Interrupt Enabled 6 OVR 0 SCI Overrun Error Interrupt Disabled 1 SCI Overrun Error Interrupt Enabled 7 RDRF 0 SCI Received Data Register Full Interrupt Disabled 1 SCI Received Data Register FullInterrupt Enabled Table 8.2 Configuration Register 1 Setting Figure 8.8. 40/99 ST52T301/E301 |
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