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ST52T301 数据表(PDF) 12 Page - STMicroelectronics |
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ST52T301 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 100 page  2.2.3 Configuration Registers The ST52x301 setting permits to configure all blocks.Table 2.2 describesthe relatedblock to each bit of the Configuration Registers. Use and meaning of each register will be described in further details in the corresponding section. Register Peripheral Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG_CONF0 PARALLEL PORT IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 REG_CONF1 SCI, CORE, I/O PORT RDRF OVR BRK TDRE TXC ECKF P8 OUT REG_CONF2 ADC not used IADD 1 ADRST REG_CONF3 SCI BRSL T8 M RE TE REG_CONF4 TIMER TMLSB REG_CONF5 TIMER TMMSB REG_CONF6 TIMER not used POL TMS CKSL TMEL IESL TMST TMRST REG_CONF7 TIMER not used FZSL INPSL INTR INTF INTSL REG_CONF8 TRIAC TCLSB REG_CONF9 TRIAC TCMSB REG_CONF10 TRIAC IOSL PSF CKSL MODE TCST TCRST REG_CONF11 TRIAC INTSL TCMSK TCTRS POL REG_CONF12 TRIAC FZSL INPSL UTPMSB REG_CONF13 TRIAC UTPLSB REG_CONF14 INTERRUPT EXTI not used MSKTC MSKTM MSKSCI MSKAD MSKE REG_CONF15 INTERRUPT INT4 INT3 INT2 INT1 Table 2.2. Configuration Registers description 12/99 ST52T301/E301 |
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