ST52T301 datasheet(10/100 Pages) STMICROELECTRONICS

部件名	ST52T301

功能描述	8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER

PDF	100 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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10 / 100 page

Figure 2.5. Input Registers Bench description

2.2.2 Input Registers Bench

The Input Registers (IR) bench consists of 11 8-bit

registers co ntaining data or status of t he

peripherals.

All the registers can be specifiedby using a decimal

address, e.g. 0 identifies the first register of the IR.

The first four registers (ADC_OUT_0:3) of the IR

are dedicated to the 4 converted values coming

from the ADC.

TMR_OUT registers contains the current counted

value by the internal Timer; whereas TMR_ST is

the Timer

status. For details about TMR_ST,

please refer to Timer description.

Data read by the Parallel I/O Port are stored

automatically in the 6-th register, INP_PORT.

Data read by the SCI are stored automatically in

the 7-th register SCI_IN and SCI status is stored in

the SCI_ST register. For details about SCI_ST,

please refer to SCI description.

The Fuzzy Core writes the computed output values

in the FUZZY_OUT_0:1 registers.

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ST52T301/E301

ST52T301 数据表(PDF) 10 Page - STMicroelectronics