ST52T301 datasheet(22/100 Pages) STMICROELECTRONICS

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at least 2

µs before updating the data and the

address.

The data updating for the next programming is

performed, directly by the user, on the data bus

P(0:7) while the address is incremented through

the pin CADD.

3.1.2 EPROM Verify

A Verify mode is available in order to verify the

correctness of the data written. It is possible to

activate the Verify mode immediately after the

writing of each byte:

CE = HIGH

OE = LOW

Then, if any error in writing occured, the user has

to repeat the EPROM writing.

The data, during this phase, are avalaible on the

bus P(0:7)

3.1.3 Writing Inhibit

It occurs between the Writing and Verify Mode:

CE = HIGH

OE = HIGH

3.1.4 Standby Mode

The EPROM has a standby mode which reduces

the active current from 10mA (Programming mode)

to less than 100

µA. The Memory is placed in

standby mode by setting CE at HIGH Logic Level

(VPP might be equal to 5 V too). When in standby

mode, the outputs are in high impedance state.

3.2 Eprom Erasure

Thanks to the transparent window present in the

CLCC44-W package, its memory contents may be

erased by exposure to UV light.

Erasure begins when the device is exposed to light

with a wavelength shorter than 4000Å.It should be

noted that sunlight, as well as some types of

ar tificial light, includes wavelengths in the

3000-4000Å range which, on prolonged exposure,

can cause erasure of memory contents. It is thus

recommended that EPROM devices be fitted with

an opaque label over the window area in order to

prevent unintentional erasure.

The recommended erasure procedure for EPROM

devices consists of exposureto short wave UV light

having a wavelength of 2537 Å. The minimum

recommended integrated dose (int ensity x

exp o- su re t im e) f or co mpl et e era su re is

15Wsec/cm 2 .

This is equivalent to an erasure time of 15-20

minutes using a UV source having an intensity of

12mW/cm 2 at a distance of 25mm (1 inch) from

the device window.

P(0:7)

DATA IN

VPP

12V

Inhibit

min 2us

2us typ.

DATA OUT

RESET

CADD

Writing

Verify

ERES

INPUT

PORT

50us typ.

OUTPUT

PORT

3us min.

Figure 3.2. EPROM Programming Timing

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ST52T301/E301

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