ST52T301 datasheet(34/100 Pages) STMICROELECTRONICS

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D7 D6 D5 D4 D3 D2 D1 D0

REG_CONF6

Timer

TMRST - Internal Timer Reset

TMST

- Internal Timer Start

not used

IESL

- Internal/External Signals Selector

TMEL

- Edge/Level Timer Abilitation

TMS

- Timer Output Shape

POL

- Timer Output Polarity

CKSL

- Internal/External Clock Select

Figure 7.6. Timer Configuration Register 6

Bit

Name

Value

Description

TMRST

Stop

Start

TMST

Stop

Start

IESL

Internal Signals

External Signals

TMEL

on Edge

on Level

CKSL

Internal Timer Clock

External Timer Clock

5TMS

Pulse Wave (Type 2)

Square Wave (Type 1)

POL

Positive Polarity

Negative Polarity

not

used

Table 7.2. Configuration Register 6 Description

CONF_REG6:

TMRST sets the internal INR signal.

TMST

sets the internal INS signal.

IESL

selects the source of the TRES and

TSTART signals.

IESL=”0” signals are the internal INR and

INS.

IESL=”1” signals come from the TRES

and TCTRL pins.

TMEL

selects the TSTART signal allowing to

work in Level Mode or in Edge Mode like

previously described.

TMEL=”0” means Edge Mode

TMEL=”1” means Level Mode.

CKSL

selects the source of the TMRCLK (work-

ing Timer frequency).

CKSL=”0”, the TMRCLK is the internal

MCLK divided by the Prescaler starting

value.

CKSL=”1”, the TMRCLK is an external

clock by TCLK pin.

TMS

TIMEROUT is a signal with frequency

equal to the working Timer frequency

divided by the starting value of the Pres-

caler (16 bit) and Counter (8 bit). The

Timer output can be either a square wave

with duty-cycle 50% or a pulse signal

(with the pulse durationequal to the Pres-

caler output signal period).

TMS=”1”, TIMEROUT is a square wave

TMS= ”0”, TIMEROUT is a pulse signal.

POL

defines the polarity of the Timer output

signal (TIMEROUT).

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