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ST52T301 数据表(PDF) 38 Page - STMicroelectronics |
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ST52T301 数据表(HTML) 38 Page - STMicroelectronics |
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38 / 100 page ![]() 8.2 INPUT HANDSHAKE Figure 8.5 illustrates the timing associated with the READY Handshake signal, when the instruction LDRI reg 6 is performed. When the LDRI instruction is executed to read the port, ST52x301 resets the READY signal to indicate that it is not possible to change the input data during this phase of reading. To synchronizethe transmission with READY signal will prevent the INP_PORT data from changing while ST52x301 is reading the port. READ PORT signal represented in figure 8.5 is an ST52x301 internal signal. Input data on the port are continuously sampled and are strobed into the port only when READY is set. W.A.R.P.3TC x x x x x x0 x REG_CONF1 P(7:0) IOP EXTERNAL PERIPHERAL DATA R EADY I/O PORT Figure 8.4. One Line Input Handshake PIO(7:0) READY DATA IN READ PORT CLK NEW DATA IN Figure 8.5. One Line Input Handshake Timing 38/99 ST52T301/E301 |
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