ST52T301 datasheet(19/100 Pages) STMICROELECTRONICS

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2.5 ARITHMETIC LOGIC UNIT

The 8-bit Arithmetic Logic Unit (ALU) allows to

per fo rm ar it hme tic calcu la tions and logic

instructions which can be divided into 4 groups:

Load, Arithmetic, Jump and Program Control

instructions (refer to the ST52x301 Assembler Set

for further details ).

Load Instructions

Menmonic

Instruction

Bytes

Cycles

LDCF

LDCF conf, const

LDRC

LDRC reg, const

LDRI

LDRI reg, inp

LDPR

LDPR per, reg

LDRR

LDRR regi, regj

Arithmetic Instructions

Mnemonic

Instruction

Bytes

Cycles

ADD

ADD regi, regj

AND

AND regi, regj

SUB

SUB regi, regj

SUBO

SUBO regi, regj

Jump Instructions

Mnemonic

Instruction

Bytes

Cycles

JP addr

JPNS

JPNS addr

JPNZ

JPNZ addr

JPS

JPS addr

JPZ

JPZ addr

SCI Instructions

Mnemonic

Instruction

Bytes

Cycles

SRX

SRX regi

STX

STX regi

Notes:

I affected

- not affected

Table 2.5. Arithmetic & Logic Instructions Set

The computation al time required for each

instruction consists of one clock pulse for each

Cycle plus 3 clock pulses for the decoding phase.

19/99

ST52T301/E301

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