ST52T301 datasheet(43/100 Pages) STMICROELECTRONICS

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Bit

Name

Value

Description

0P8

Digital Output Bit

ECKF

5 MHz

10 MHz

20 MHz

TXC

SCI End Transmission

Interrupt Disabled

SCI End Transmission

Interrupt Enabled

TDRE

SCI Transmission Data

Disabled

SCI Transmission Data

Enabled

BRK

SCI Break Error Interrupt

Disabled

SCI Break Error Interrupt

Enabled

OVR

SCI Overrun Error Interrupt

Disabled

SCI Overrun Error Interrupt

Enabled

RDRF

SCI Received Data Register

Full Interrupt Disabled

SCI Received Data Register

FullInterrupt Enabled

Table 9.2 Configuration Register 1 Setting

The analysis of RxD input signal is carried out

looking three samples for each bits received.0

If these three samples are not equal, then the noise

error flag, NSERR, of Input Register 8 is set to 1

and the received data value will be the one

assumed by the majority of the samples.

By means of the procedure described above, to

avoid SCI becomes IDLE, because of a limited

noise due t o an erroneous sampling, th e

transmissionis recognizedas correct and the noise

flag error is set.

At the end of the cycle relative to the reception of

a bit, Recovery Buffer Block will repeat the same

steps 9 times: one step for each received bit, plus

one for the stop acquisition(10 times in case of 9-bit

data, double stop or parity check).

At the end of datareception,Recovery BufferBlock,

will supply information on eventual frame errors by

setting to 1 FRERR flag bit of Input Register 8.

A frame error can occur if the parity check has not

been successfully achieved or if STOP bit has not

been detected.

If Recovery Buffer Block receives 10 consecutive

bits at logic level 0, a break error occurres, and

interrupt routine request starts.

SCDR_RX block

It is a finite state machine synchronized with the

falling edge of the clock master signal, CKM.

The SCDR_RX block waits the signal of complete

reception, from the Recovery Buffer, to load the

word received. Moreover, the SCDR_RCX block

loads the values of FRERR and NSERR flag bits

(Input Register 8), and sets the RXF flag to 1.

Using SRX instruction the data are transferred to

SCDR_RX block is empty.

If a new data arrives before the previous one has

been transferred to Register File, an overrun error

occurres and OVERR flag, of Input Register 8, is

set to 1.

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ST52T301/E301

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