ST52T301 datasheet(44/100 Pages) STMICROELECTRONICS

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9.2 SCI TRANSMITTER BLOCK

The SCI Transmitter Block consists of the following

underblocks: SCDR_TX and SHIFT REGISTER,

synchronized, respectively, with the clock master

signal (CKM) and the CLOCK_TX.

The whole block receives through Configuration

transmission modes (see table 9.1):

8-bit word and a single stop signal

8-bit word plus a paritybit and a singlestop signal

8-bit word plus a double stop signal

9-bit word

In case of 9 bit frame transmission, the most

significat ive bit arrives through T8 of th e

Configuration Register 3.

In an 8-bit transmission, instead, T8 is used to

configure the SCI, according to informat ion

containedin M (see table 9.1):in particularto chose

the polarity control (even or odds) to implement the

parity check.

After a RESET signal, RST, the SCDR_TX block is

in IDLE state until it receivesenabling signal, TE=1,

of Configuration Register 3.

If TE=1, using STX instruction the data, to be

transmitted, are transferred from Register File to

SCDR_TX block and the flag of Input Register 8,

TXEM, is reset to 0, to indicate SCDR_TX block is

full.

If the core supplies a new data, this could not be

loaded in the SCDR_TX block until the current data

has not been unloaded on the Shift Register block.

This means that only when TXEM is 1, it is possible

to load data in the SCDR_TX Block.

When the SHIFT REGISTER Block loads the data

to be transmitted on an internal buffer, TXEND is

reset to 0 to indicate the beginning of a new

transmission. At the end of transmission TXEND is

set to 1, allowing to load in the SHIFT REGISTER

a new data coming from SCDR_TX.

It is important to underline that TXEND = 1 does

not mean SCDR_TX is ready to receivea newdata.

For this reason it is better to utilise the TXEM signal

to synchronize the STX instruction to the SCI

TRANSMITTER block

If ST52x301 core resets TE to 0, the transmission

is inte rrupted, but the SCI Transmitter block

completes the transmission in progress before to

reset.

9.3 Baud Rate Generator Block

The Baud Rate Generator Block performs the

division of the clock master signal (CKM), in a set

of synchronism frequencies for the serial bit

reception/transmission on the external line.

Table 9.1. shows the set of frequenciesselected by

means of BRSL (Configuration Register 3).

Reception frequency (CLOCK_RX) is 16 times

higher than transmission frequency (CLOCK_TX) .

If BRSL is equal to 111, CLOCK_RX and

CLOCK_TX signals coincide with clock master,

CKM.

Figure 9.3. SCI Status Input Register

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ST52T301/E301

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