ST92F120JR9T datasheet(79/320 Pages) STMICROELECTRONICS

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ST92F120 - INTERRUPTS

5.6 EXTERNAL INTERRUPTS

5.6.1 Standard External Interrupts

The standard ST9 core contains 8 external inter-

rupts sources grouped into four pairs.

Table 19. External Interrupt Channel Grouping

Each source has a trigger control bit TEA0,..TED1

(R242,EITR.0,..,7 Page 0) to select triggering on

the rising or falling edge of the external pin. If the

Trigger control bit is set to “1”, the corresponding

pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page

0) is set on the input pin rising edge, if it is cleared,

the pending bit is set on the falling edge of the in-

put pin. Each source can be individually masked

through

the

corresponding

control

bit

IMA0,..,IMD1 (EIMR.7,..,0). See Figure 39.

Figure 38. Priority Level Examples

The priority level of the external interrupt sources

can be programmed among the eight priority lev-

els with the control register EIPLR (R245). The pri-

ority level of each pair is software defined using

the bits PRL2,PRL1. For each pair, the even chan-

nel (A0,B0,C0,D0) of the group has the even prior-

ity level and the odd channel (A1,B1,C1,D1) has

the odd (lower) priority level.

Figure 38 shows an example of priority levels.

Figure 39 gives an overview of the external inter-

rupts and vectors.

– The source of interrupt channel A0 can be se-

lected between the external pin INT0 or the

Timer/Watchdog peripheral using the IA0S bit in

the EIVR register (R246 Page 0).

– The source of interrupt channel A1 can be se-

lected between the external pin INT1 or the

Standard Timer using the INTS bit in the STC

– The source of the interrupt channel B0 can be

selected between the external pin INT2 or the

on-chip Extended Function Timer 0 using the

EFTIS bit in the CR3 register (R255 Page 28).

– The source of interrupt channel B1 can be se-

lected between external pin INT3 or the on-chip

Extended Function Timer 1 using the EFTIS bit

in the CR3 register (R255 Page 29).

– The source of the interrupt channel C0 can be

selected between external pin INT4 or the On-

chip EEPROM/Flash Memory using bit FEIEN

in the ECR register (Address 224001h).

– The source of interrupt channel C1 can be se-

lected between external pin INT5 or the on-chip

SPI using the SPIS bit in the SPCR0 register

(R241 Page 7).

– The source of interrupt channel D0 can be se-

lected between external pin INT6 or the Reset

and Clock Unit RCCU using the INT_SEL bit in

the CLKCTL register (R240 Page 55).

– The source of interrupt channel D1 selected be-

tween the NMI pin and the WUIMU Wakeup/In-

terrupt Lines using the ID1S bit in the WUCRTL

Warning: When using external interrupt channels

shared by both external interrupts and peripherals,

special care must be taken to configure control

registers both for peripheral and interrupts.

External

Interrupt

Channel

I/O Port Pin

WKUP[0:15]

INTD1

P8[1:0] P7[7:5]

P6[7,5] P5[7:5, 2:0] P4[7,4]

INT6

INT5

INT4

INT3

INT2

INT1

INT0

INTD0

INTC1

INTC0

INTB1

INTB0

INTA1

INTA0

P6.1

P6.3

P6.2

P6.3

P6.2

P6.0

100

PL2D PL1D PL2 C PL1C PL2 B PL1B PL2 A PL1 A

INT.D1:

INT.C1: 001=1

INT.D0:

SOURCE

PRIORITY

SOURCE

INT.A0: 010=2

INT.A1: 011=3

INT.B1: 101=5

INT.B0: 100=4

INT.C0: 000=0

EIPLR

VR00015 1

100=4

101=5

Channel

Internal Interrupt Source

External

Interrupt

Source

INTA0

Timer/Watchdog

INT0

INTA1

Standard Timer

INT1

INTB0

Extended Function Timer 0

INT2

INTB1

Extended Function Timer 1

INT3

INTC0

EEPROM/Flash

INT4

INTC1

SPI Interrupt

INT5

INTD0

RCCU

INT6

INTD1

Wake-up Management Unit

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