ST92F120JR9T datasheet(18/320 Pages) STMICROELECTRONICS

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ST92F120 - GENERAL DESCRIPTION

Table 1. ST92F120 Power Supply Pins

Table 2. ST92F120 Primary Function Pins

Figure 10. Recommended connections for VREG

Note : For future compatibility with shrinked versions, the VREG pins should be connected to a minimum

of 600 nF (total). Special care should be taken to minimize the distance between the ST9 microcontroller

and the capacitors.

Name

Function

VDD

Main Power Supply Voltage

( pins internally connected)

-18

-65

VSS

Digital Circuit Ground

(pins internally connected)

-17

-64

AVDD

Analog Circuit Supply Voltage

AVSS

Analog Circuit Ground

VPP

Must be kept low in standard

operating mode

VREG

3V regulator output

Name

Fun ction

Address Strobe

Data Strobe

Read/Write

OSCIN

Oscillator Input

OSCOUT

Oscillator Output

RESET

Reset to initialize the Micro-

controller

HW0SW1

Watchdog HW/SW enabling

selection

VPWO

J1850 JBLPD Output. On

devices without JBPLD pe-

ripheral, this pin must not be

connected.

300 nF

QFP100

QFP 64

600 nF

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