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ST92F120JR9T 数据表(PDF) 37 Page - STMicroelectronics |
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ST92F120JR9T 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 320 page  37/320 ST92F120 - DEVICE ARCHITECTURE 2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within group F, Page 21 of the Register File. The 7 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data Memory ac- cesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA trans- fers (DMASR or ISR). Figure 19. Page 21 Registers DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h MMU EM Page 21 MMU MMU Bit DPRREM=0 SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 1 DPR0 Bit DPRREM=1 SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 Relocation of P[3:0] and DPR[3:0] Registers (default setting) 9 |
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