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ST92F120JR9T 数据表(PDF) 19 Page - STMicroelectronics

部件名 ST92F120JR9T
功能描述  8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD
PDF  320 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST92F120JR9T 数据表(HTML) 19 Page - STMicroelectronics

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ST92F120 - GENERAL DESCRIPTION
1.3 I/O PORTS
Port 0 and Port 1 provide the external memory in-
terface. All the ports of the device can be pro-
grammed as Input/Output or in Input mode, com-
patible with TTL or CMOS levels (except where
Schmitt Trigger is present). Each bit can be pro-
grammed individually (Refer to the I/O ports chap-
ter).
Internal Weak Pull-up
As shown in Table 3, not all input sections imple-
ment a Weak Pull-up. This means that the pull-up
must be connected externally when the pin is not
used or programmed as bidirectional.
TTL/CMOS Input
For all those port bits where no input schmitt trig-
ger is implemented, it is always possible to pro-
gram the input level as TTL or CMOS compatible
by programming the relevant PxC2.n control bit.
Refer I/O Ports Chapter to the section titled “Input/
Output Bit Configuration”.
Schmitt Trigger Input
Two different kind of Schmitt Trigger circuitries are
implemented: Standard and High Hysteresis.
Standard Schmitt Trigger is widely used (see Ta-
ble 3), while the High Hysteresis one is present on
the NMI and VPWI input function pins mapped on
Port 6 [5:4] (see Table 4).
All inputs which can be used for detecting interrupt
events have been configured with a “standard”
Schmitt Trigger, apart from, as already said, the
NMI pin which implements the “High Hysteresis”
version. In this way, all interrupt lines are guaran-
teed as “level sensitive”.
Push-Pull/OD Output
The output buffer can be programmed as push-
pull or open-drain: attention must be paid to the
fact that the open-drain option corresponds only to
a disabling of P-channel MOS transistor of the
buffer itself: it is still present and physically con-
nected to the pin. Consequently it is not possible to
increase the output voltage on the pin over
VDD+0.3 Volt, to avoid direct junction biasing.
Pure Open-drain Output
The user can increase the voltage on an I/O pin
over VDD+0.3 Volt where the P-channel MOS tran-
sistor is physically absent: this is allowed on all
“Pure Open Drain” pins. Of course, in this case the
push-pull option is not available and any weak
pull-up must implemented externally.
Table 3. I/O Port Characteristics
Legend: WPU = Weak Pull-Up, OD = Open Drain
Input
Outpu t
Weak Pull-Up
Reset State
Port 0[7:0]
TTL/CMOS
Push-Pull/OD
No
Bidirectional
Port 1[7:0]
TTL/CMOS
Push-Pull/OD
No
Bidirectional
Port 2[1:0]
Port 2[3:2]
Port 2[5:4]
Port 2[7:6]
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
Push-Pull/OD
Pure OD
Push-Pull/OD
Push-Pull/OD
Yes
No
Yes
Yes
Input
Input CMOS
Input
Input CMOS
Port 3[2:1]
Port 3.3
Port 3[7:4]
Schmitt trigger
TTL/CMOS
Schmitt trigger
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Yes
Yes
Yes
Input
Input CMOS
Input
Port 4.0, Port 4.4
Port 4.1
Port 4.2, Port 4.5
Port 4.3
Port 4[7:6]
Schmitt trigger
TTL/CMOS
TTL/CMOS
Schmitt trigger
Schmitt trigger inside I/O cell
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Pure OD
No
Yes
Yes
Yes
No
Input
Bidirectional WPU
Input CMOS
Input
Input
Port 5[2:0], Port [7:4]
Port 5.3
Schmitt trigger
TTL/CMOS
Push-Pull/OD
Push-Pull/OD
No
Yes
Input
Input CMOS
Port 6[3:0]
Port 6[5:4]
Schmitt trigger
High hysteresis Schmitt trigger
inside I/O cell
Push-Pull/OD
Push-Pull/OD
Yes
Yes (inside I/O cell)
Input
Input
Port 7[7:0]
Schmitt trigger
Push-Pull/OD
Yes
Input
Port 8[1:0]
Port 8[7:2]
Schmitt trigger
Schmitt trigger
Push-Pull/OD
Push-Pull/OD
Yes
Yes
Input
Bidirectional WPU
Port 9[7:0]
Schmitt trigger
Push-Pull/OD
Yes
Bidirectional WPU
9



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