ST92F120JR9T datasheet(99/320 Pages) STMICROELECTRONICS

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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

7 RESET AND CLOCK CONTROL UNIT (RCCU)

7.1 INTRODUCTION

The Reset and Clock Control Unit (RCCU) com-

prises two distinct sections:

– the Clock Control Unit, which generates and

manages the internal clock signals.

– the Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog gener-

ated resets.

On ST9 devices where the external Stop pin is

available, this circuit also detects and manages

the externally triggered Stop mode, during which

all oscillators are frozen in order to achieve the

lowest possible power consumption.

7.2 CLOCK CONTROL UNIT

The Clock Control Unit generates the internal

clocks for the CPU core (CPUCLK) and for the on-

chip peripherals (INTCLK). The Clock Control Unit

may be driven by an external crystal circuit, con-

nected to the OSCIN and OSCOUT pins, or by an

external pulse generator, connected to OSCIN

(see Figure 51 and Figure 53). A low frequency ex-

ternal clock may be connected to the CK_AF pin,

and this clock source may be selected when low

power operation is required.

7.2.1 Clock Control Unit Overview

As shown in Figure 45 a programmable divider

can divide the CLOCK1 input clock signal by two.

In practice, the divide-by-two is virtually always

used in order to ensure a 50% duty cycle signal to

the PLL multiplier circuit. The resulting signal,

CLOCK2, is the reference input clock to the pro-

grammable Phase Locked Loop frequency multi-

plier, which is capable of multiplying the clock fre-

quency by a factor of 6, 8, 10 or 14; the multiplied

clock is then divided by a programmable divider,

by a factor of 1 to 7. By this means, the ST9 can

operate with cheaper, medium frequency (3-5

MHz) crystals, while still providing a high frequen-

cy internal clock for maximum system perform-

ance; the range of available multiplication and divi-

sion factors allow a great number of operating

clock frequencies to be derived from a single crys-

tal frequency.

For low power operation, especially in Wait for In-

terrupt mode, the Clock Multiplier unit may be

turned off, whereupon the output clock signal may

be programmed as CLOCK2 divided by 16. For

further power reduction, a low frequency external

clock connected to the CK_AF pin may be select-

ed, whereupon the crystal controlled main oscilla-

tor may be turned off.

The internal system clock, INTCLK, is routed to all

on-chip peripherals, as well as to the programma-

ble Clock Prescaler Unit which generates the clock

for the CPU core (CPUCLK). (See Figure 45)

The Clock Prescaler is programmable and can

slow the CPU clock by a factor of up to 8, allowing

the programmer to reduce CPU processing speed,

and thus power consumption, while maintaining a

high speed clock to the peripherals. This is partic-

ularly useful when little actual processing is being

done by the CPU and the peripherals are doing

most of the work.

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