ST92F120JR9T datasheet(49/320 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

Bit 2 = WFIS:

Wait For Interrupt Status.

If this bit is reset, the WFI instruction puts the

Flash macrocell in Stand-by mode (immediate

read possible, but higher consumption: 100

µA); if

it is set, the WFI instruction puts the Flash macro-

cell in Power-Down mode (recovery time of 10

µs

needed before reading, but lower consumption:

µA). The Stand-by mode or the Power-Down

mode will be entered only at the end of any current

Flash or EEPROM write operation.

In the same way following an HALT or a STOP in-

struction, the Memory enters Power-Down mode

only after the completion of any current write oper-

ation.

0: Flash in Standby mode on WFI

1: Flash in Power-Down mode on WFI

Note: HALT or STOP mode can be exited without

problems, but the user should take care when ex-

iting WFI Power Down mode. If WFIS is set, the

user code must reset the XT_DIV16 bit in the

R242 register (page 55) before executing the WFI

instruction. When exiting WFI mode, this gives the

Flash enough time to wake up before the interrupt

vector fetch.

Bit 1 = FEIEN:

Flash & EEPROM Interrupt enable.

This bit selects the source of interrupt channel

INTx between the external interrupt pin and the

Flash/EEPROM End of Write interrupt. Refer to

the Interrupt chapter for the channel number.

0: External interrupt enabled

1: Flash & EEPROM Interrupt enabled

Bit 0 = EBUSY:

EEPROM Busy (Read Only).

This bit is automatically set during a Page Update

operation when the first address to be modified is

latched in the EEPROM memory, or during Chip

Erase operation when bit EWMS is set. At the end

of the write operation or during a Sector Erase

Suspend this bit is automatically reset and the

memory returns to read mode. When this bit is set

every read access to the EEPROM memory will

output invalid data (FFh equivalent to a NOP in-

struction), while every write access to the EEP-

ROM memory will be ignored. At the end of the

write operation this bit is automatically reset and

the memory returns to read mode. EBUSY rises

also if a write operation is started in one of the two

EEPROM sectors, used as Flash sectors. Bit

EBUSY remains high for a maximum of 10ms after

Power-Up and when exiting Power-Down mode,

meaning that the EEPROM memory is not yet

ready to be accessed.

0: EEPROM not busy

1: EEPROM busy

ST92F120JR9T 数据表(PDF) 49 Page - STMicroelectronics

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