ST92F120JR9T datasheet(57/320 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

3.6.2 Temporary Unprotection

On user request the memory can be configured so

as to allow the temporary unprotection also of all

access protections bits of NVAPR (write protection

bits of NVWPR are always temporarily unprotecta-

ble).

Bit APEX can be temporarily disabled by execut-

ing the Set Protection operation and writing 1 into

this bit, but only if this write instruction is executed

from an internal memory (Flash and Test Flash ex-

cluded).

Bit APEE can be temporarily disabled by execut-

ing the Set Protection operation and writing 1 into

this bit, but only if this write instruction is executed

from the memory itself to unprotect (EEPROM).

Bits APRO and APBR can be temporarily disabled

through a direct write at NVAPR location, by over-

writing at 1 these bits, but only if this write instruc-

tion is executed from the memory itself to unpro-

tect.

To restore the access protection bits it needs to re-

set the micro or to execute a Set Protection opera-

tion and write 0 into the desired bits.

When an internal memory (Flash, TestFlash or

EEPROM) is protected in access, also the data ac-

cess through a DMA of a peripheral is forbidden (it

returns FFh). To read data in DMA mode from a

protected memory, first it is necessary to tempo-

rarily unprotect that memory.

The temporary unprotection allows also to update

a protected code.

3.7 FLASH IN-SYSTEM PROGRAMMING

The Flash memory can be programmed in-system

through a serial interface (SCI0).

Exiting from reset, the ST9 executes the initializa-

tion from the BootROM code (written in Test-

Flash), where it checks the value of the SOUT0

pin. If it is at 0, this means that the user wishes to

update the Flash code, otherwise normal execu-

tion continues. In this second case, the BootROM

code reads the first two locations of the Flash

memory (000000h-000001h) that represent the

pointer to the start of the user code.

If the Flash is virgin (read content is always FFh),

its first two locations contain FFFFh. This will rep-

resent the last location of segment 0h, and it is in-

terpreted by the BootROM code as a flag indicat-

ing that the Flash memory is virgin and needs to

be programmed. If the value 1 is detected on the

SOUT0 pin and the Flash is virgin, a HALT instruc-

tion is executed, waiting for a hardware Reset.

3.7.1 First Programming of a virgin Flash

After checking that the SOUT0 pin is at 0, the Boot

-ROM code enables the serial interface (typically

an SCI) and writes in its Address Compare Regis-

ter (ACR for SCI) a predefined address for recog-

nition. The BootROM initializes the serial interface,

including the interrupt vector table in the TestFlash

itself, the Interrupt Vector Register for the serial in-

terface (IVR for SCI), the mask bit to enable the

address match interrupt (bit RXA of IMR for SCI).

When the serial interface has received an address

matching with the content of its Address Compare

fined routine is executed located in TestFlash

(Code Update Routine), that loads at a predefined

address in the internal RAM a predefined number

of bytes (the first datum sent) from the serial inter-

face.

These bytes must represent a routine (the in-sys-

tem programming routine) which is called at the

end of the transfer.

This routine can, for example, load in the internal

RAM (through the serial interface in DMA mode) a

first table of data (256 bytes for example; depend-

ing on the available internal RAM size) to be pro-

grammed in Flash. Then the routine starts to pro-

gram the Flash memory using the first table, while,

in parallel, a second table of data are loaded in an-

other location of the internal RAM, through the se-

rial interface. When the slower of these two paral-

lel operations is ended, a new cycle can start, till

the whole Flash memory is programmed.

At the end of Flash programming the execution re-

turns to the Code Update Routine in TestFlash

that puts the ST9 in HALT mode, waiting for a

hardware reset.

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