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ST92F120 - DEVICE ARCHITECTURE

MMU REGISTERS (Cont’d)

2.7.2 CSR: Code Segment Register

This register selects the 64-Kbyte code segment

being used at run-time to access instructions. It

can also be used to access data if the spm instruc-

tion has been executed (or ldpp, ldpd, lddp).

Only the 6 LSBs of the CSR register are imple-

mented, and bits 6 and 7 are reserved. The CSR

divided into 64 segments of 64 Kbytes.

To generate the 22-bit Program memory address,

the contents of the CSR register is directly used as

the 6 MSBs, and the 16-bit virtual address as the

16 LSBs.

Note: The CSR register should only be read and

not written for data operations (there are some ex-

ceptions which are documented in the following

paragraph). It is, however, modified either directly

by means of the jps and calls instructions, or

indirectly via the stack, by means of the rets in-

struction.

CODE SEGMENT REGISTER (CSR)

R244 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7:6 = Reserved, keep in reset state.

Bit 5:0 = CSR_[5:0]: These bits define the 64-

Kbyte memory segment (among 64) which con-

tains the code being executed. These bits are

used as the most significant address bits (A21-16).

2.7.3 ISR: Interrupt Segment Register

INTERRUPT SEGMENT REGISTER (ISR)

R248 - Read/Write

Reset value: undefined

ISR and ENCSR bit (EMR2 register) are also de-

scribed in the chapter relating to Interrupts, please

refer to this description for further details.

Bit 7:6 = Reserved, keep in reset state.

Bit 5:0 = ISR_[5:0]: These bits define the 64-Kbyte

memory segment (among 64) which contains the

interrupt vector table and the code for interrupt

service routines and DMA transfers (when the PS

bit of the DAPR register is reset). These bits are

used as the most significant address bits (A21-16).

The ISR is used to extend the address space in

two cases:

– Whenever an interrupt occurs: ISR points to the

64-Kbyte memory segment containing the inter-

rupt vector table and the interrupt service routine

code. See also the Interrupts chapter.

– During DMA transactions between the peripheral

and memory when the PS bit of the DAPR regis-

ter is reset : ISR points to the 64 K-byte Memory

segment that will be involved in the DMA trans-

action.

2.7.4 DMASR: DMA Segment Register

DMA SEGMENT REGISTER (DMASR)

R249 - Read/Write

Reset value: undefined

Bit 7:6 = Reserved, keep in reset state.

Bit 5:0 = DMASR_[5:0]: These bits define the 64-

Kbyte Memory segment (among 64) used when a

DMA transaction is performed between the periph-

eral’s data register and Memory, with the PS bit of

the DAPR register set. These bits are used as the

most significant address bits (A21-16). If the PS bit

is reset, the ISR register is used to extend the ad-

dress.

CSR_

ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0

DMA

SR_5

DMA

SR_4

DMA

SR_3

DMA

SR_2

DMA

SR_1

DMA

SR_0

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