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ST92F120JR9T 数据表(PDF) 36 Page - STMicroelectronics |
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ST92F120JR9T 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 320 page  36/320 ST92F120 - DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ST9+ provides a total addressable memory space of 4 Mbytes. This address space is ar- ranged as 64 segments of 64 Kbytes; each seg- ment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (inter- nal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map. 9 |
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