ST92F120JR9T datasheet(46/320 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

FUNCTIONAL DESCRIPTION (Cont’d)

Table 9. Memory Structure for 36K Flash device

3.2.3 Operation

The memory has a register interface mapped in

memory space (segment 22h). All operations are

enabled through the FCR (Flash Control Register)

ECR (EEPROM Control Register).

All operations on the Flash must be executed from

another memory (internal RAM, EEPROM, exter-

nal memory).

Flash (including TestFlash) and EEPROM have

duplicated sense amplifiers, so that one can be

read while the other is written. However simultane-

ous Flash and EEPROM write operations are for-

bidden.

An interrupt can be generated at the end of a

Flash or an EEPROM write operation: this inter-

rupt is multiplexed with an external interrupt EX-

TINTx (device dependent) to generate an interrupt

INTx.

The status of a write operation inside the Flash

and the EEPROM memories can be monitored

through the FESR[1:0] registers.

Control and Status registers are mapped in mem-

ory (segment 22h), as shown in the following fig-

ure.

Figure 24. Control and Status Register Map.

During a write operation, if the power supply drops

or the RESET pin is activated, the write operation

is immediately interrupted. In this case the user

must repeat the last write operation following pow-

er on or reset.

Sector

Addresses

Max Size

TestFlash (TF) (Reserved)

230000h to 230F7Fh

3968 bytes

User OTP Area

231F80h to 230FFFh

128 bytes

Flash 0 (F0)

000000h to 000FFFh

4 Kbytes

Flash 1 (F1)

010000h to 013FFFh

16 Kbytes

Flash 2 (F2)

014000h to 015FFFh

8 Kbytes

Flash 3 (F3)

016000h to 017FFFh

8 Kbytes

Flash 4 / EEPROM 0 (F4/E0)

228000h to 2287FFh

2 Kbytes

Flash 5 / EEPROM 1 (F5/E1)

22C000h to 22C7FFh

2 Kbytes

Emulated EEPROM

220000h to 2201FFh

512 bytes

224000h

224001h

224002h

FCR

ECR

FESR0

FESR1

224003h

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