ST92F120JR9T datasheet(85/320 Pages) STMICROELECTRONICS

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ST92F120 - INTERRUPTS

INTERRUPT REGISTERS (Cont’d)

EXTERNAL INTERRUPT VECTOR REGISTER

(EIVR)

R246 - Read/Write

Reset value: xxxx 0110b (x6h)

Bit 7:4 = V[7:4]:

Most significant nibble of External

Interrupt Vector.

These bits are not initialized by reset. For a repre-

sentation of how the full vector is generated from

V[7:4] and the selected external interrupt channel,

refer to Figure 39.

Bit 3 = TLTEV:

Top Level Trigger Event bit.

This bit is set and cleared by software.

0: Select falling edge as NMI trigger event

1: Select rising edge as NMI trigger event

Bit 2 = TLIS:

Top Level Input Selection.

This bit is set and cleared by software.

0: Watchdog End of Count is TL interrupt source

1: NMI is TL interrupt source

Bit 1 = IA0S:

Interrupt Channel A0 Selection.

This bit is set and cleared by software.

0: Watchdog End of Count is INTA0 source

1: External Interrupt pin is INTA0 source

Bit 0 = EWEN:

External Wait Enable.

This bit is set and cleared by software.

0: WAITN pin disabled

1: WAITN pin enabled (to stretch the external

memory access cycle).

Note: For more details on Wait mode refer to the

section describing the WAITN pin in the External

Memory Chapter.

NESTED INTERRUPT CONTROL (NICR)

R247 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = TLNM:

Top Level Not Maskable.

This bit is set by software and cleared only by a

hardware reset.

0: Top Level Interrupt Maskable. A top level re-

quest is generated if the IEN, TLI and TLIP bits

1: Top Level Interrupt Not Maskable. A top level

request is generated if the TLIP bit =1

Bit 6:0 = HL[6:0]:

Hold Level x

These bits are set by hardware when, in Nested

Mode, an interrupt service routine at level x is in-

terrupted from a request with higher priority (other

than the Top Level interrupt request). They are

cleared by hardware at the iret execution when

the routine at level x is recovered.

TLTEV TLIS IAOS EWEN

TLNM HL6

HL5

HL4

HL3

HL2

HL1

HL0

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