ST92F120JR9T datasheet(56/320 Pages) STMICROELECTRONICS

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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM

PROTECTION STRATEGY (Cont’d)

Bit 2:0 = PWT[2:0]:

Password Attempt 2-0.

If the TMDIS bit in the NVWPR register (231FFDh)

is programmed to 0, every time a Set Protection

operation is executed with Program Addresses

equal to NVPWD1-0 (231FFE-Fh), the two provid-

Program

Data

are

compared

with

the

NVPWD1-0 content; if there is not a match one of

PWT2-0 bits is automatically programmed to 0:

when these three bits are all programmed to 0 the

test modes are disabled forever. In order to inten-

tionally disable test modes forever, it is sufficient to

set a random Password and then to make 3 wrong

attempts to enter it.

NON VOLATILE WRITE PROTECTION REGIS-

TER (NVWPR)

Address: 231FFDh - Read/Write

Delivery value: 1111 1111 (FFh)

Bit 7 = TMDIS:

Test mode disable (Read Only).

This bit, if set to 1, allows to bypass all the protec-

tions in test mode. If programmed to 0, on the con-

trary, all the protections remain active also in test

mode. The only way to enable the test modes if

this bit is programmed to 0, is to execute the Set

Protection operation with Program Addresses

equal to NVPWD1-0 (231FFF-Eh) and Program

Data matching with the content of NVPWD1-0.

This bit is read only: it is automatically pro-

grammed to 0 when NVPWD1-0 are written.

0: Test mode disabled

1: Test mode enabled

Bit 6 = PWOK:

Password OK (Read Only).

If the TMDIS bit is programmed to 0, when the Set

Protection operation is executed with Program Ad-

dresses equal to NVPWD[1:0] and Program Data

matching with NVPWD[1:0] content, the PWOK bit

is automatically programmed to 0. When this bit is

programmed to 0 TMDIS protection is bypassed

and the test modes are enabled.

0: Password OK

1: Password not OK

Bit 5 = WPBR:

BootROM Write Protection.

This bit, if programmed at 0, disables any write ac-

cess to the TestFlash address space. This protec-

tion cannot be temporarily disabled.

0: BootROM write protection on

1: BootROM write protection off

Bit 4 = WPEE:

EEPROM Write Protection.

This bit, if programmed to 0, disables any write ac-

cess to the EEPROM address space. This protec-

tion can be temporary disabled by executing the

Set Protection operation and writing 1 into this bit.

To restore the protection it needs to reset the mi-

cro or to execute another Set Protection operation

and write 0 to this bit.

0: EEPROM write protection on

1: EEPROM write protection off

Bit 3:0 = WPRS[3:0]:

ROM Segments 3-0 Write

Protection.

These bits, if programmed to 0, disable any write

access to the 4 Flash sectors address spaces.

These protections can be temporary disabled by

executing the Set Protection operation and writing

1 into these bits. To restore the protection it needs

to reset the micro or to execute another Set Pro-

tection operation and write 0 into these bits.

0: ROM Segments 3-0 write protection on

1: ROM Segments 3-0 write protection off

NON VOLATILE PASSWORD (NVPWD1-0)

Address: 231FFF-231FFEh - Write Only

Delivery value: 1111 1111 (FFh)

Bit 7:0 = PWD[7:0]:

Password bits 7:0 (Write On-

ly).

These bits must be programmed with the Non Vol-

atile Password that must be provided with the Set

Protection operation to reenable the test modes.

These two registers can be accessed only in write

mode and only once; when they are written (simul-

taneously with the same Set Protection operation),

bit TMDIS of NVWPR (231FFDh) is simultaneous-

ly programmed and test modes are disabled.

TMDI

PWO

WPB

WPE

WPRS

765432

PWD

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