ST92F120JR9T datasheet(102/320 Pages) STMICROELECTRONICS

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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

7.3.1 PLL Clock Multiplier Programming

The CLOCK1 signal generated by the oscillator

drives a programmable divide-by-two circuit. If the

DIV2 control bit in MODER is set (Reset Condi-

tion), CLOCK2, is equal to CLOCK1 divided by

two; if DIV2 is reset, CLOCK2 is identical to

CLOCK1. Since the input clock to the Clock Multi-

plier circuit requires a 50% duty cycle for correct

PLL operation, the divide by two circuit should be

enabled when a crystal oscillator is used, or when

the external clock generator does not provide a

50% duty cycle. In practice, the divide-by-two is

virtually always used in order to ensure a 50% duty

cycle signal to the PLL multiplier circuit.

When the PLL is active, it multiplies CLOCK2 by 6,

8, 10 or 14, depending on the status of the MX0 -1

bits in PLLCONF. The multiplied clock is then di-

vided by a factor in the range 1 to 7, determined by

the status of the DX0-2 bits; when these bits are

programmed to 111, the PLL is switched off.

Following a RESET phase, programming bits

DX0-2 to a value different from 111 will turn the

PLL on. To select the multiplier clock, set the

CSU_CKSEL bit in the CLK_FLAG Register after

allowing a stabilisation period for the PLL.

Care is required, when programming the PLL mul-

tiplier and divider factors, not to exceed the maxi-

mum permissible operating frequency for INTCLK,

according to supply voltage, as reported in Electri-

cal Characteristics section.

The ST9 being a static machine, there is no lower

limit for INTCLK. However, some peripherals have

their own minimum internal clock frequency limit

below which the functionality is not guaranteed.

7.3.2 CPU Clock Prescaling

The system clock, INTCLK, which may be the out-

put of the PLL clock multiplier, CLOCK2, CLOCK2/

16 or CK_AF, drives a programmable prescaler

which generates the basic time base, CPUCLK,

for the instruction executer of the ST9 CPU core.

This allows the user to slow down program execu-

tion during non processor intensive routines, thus

reducing power dissipation.

The internal peripherals are not affected by the

CPUCLK prescaler and continue to operate at the

full INTCLK frequency. This is particularly useful

when little processing is being done and the pe-

ripherals are doing most of the work.

The prescaler divides the input clock by the value

programmed in the control bits PRS2,1,0 in the

MODER register. If the prescaler value is zero, no

prescaling takes place, thus CPUCLK has the

same period and phase as INTCLK. If the value is

different from 0, the prescaling is equal to the val-

ue plus one, ranging thus from two (PRS2,1,0 = 1)

to eight (PRS2,1,0 = 7).

The clock generated is shown in Figure 47, and it

will be noted that the prescaling of the clock does

not preserve the 50% duty cycle, since the high

level is stretched to replace the missing cycles.

This is analogous to the introduction of wait cycles

for access to external memory. When External

Memory Wait or Bus Request events occur, CPU-

CLK is stretched at the high level for the whole pe-

riod required by the function.

Figure 47. CPU Clock Prescaling

INTCLK

CPUCLK

VA00260

000

001

010

011

100

101

110

111

PRS VALUE

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