ST92F120JR9T datasheet(103/320 Pages) STMICROELECTRONICS

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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

7.3.3 Peripheral Clock

The system clock, INTCLK, which may be the out-

put of the PLL clock multiplier, CLOCK2, CLOCK2/

16 or CK_AF, is also routed to all ST9 on-chip pe-

ripherals and acts as the central timebase for all

timing functions.

7.3.4 Low Power Modes

The user can select an automatic slowdown of

clock frequency during Wait for Interrupt opera-

tion, thus idling in low power mode while waiting

for an interrupt. In WFI operation the clock to the

CPU core is stopped, thus suspending program

execution, while the clock to the peripherals may

be programmed as described in the following par-

agraphs. Two examples of Low Power operation in

WFI are illustrated in Figure 48 and Figure 49.

Providing that low power operation during Wait for

Interrupt is enabled (by setting the LPOWFI bit in

the CLKCTL Register), as soon as the CPU exe-

cutes the WFI instruction, the PLL is turned off and

the system clock will be forced to CLOCK2 divided

by 16, or to the external low frequency clock,

CK_AF, if this has been selected by setting

WFI_CKSEL, and providing CKAF_ST is set, thus

indicating that the external clock is selected and

actually present on the CK_AF pin.

If the external clock source is used, the crystal os-

cillator may be stopped by setting the XTSTOP bit,

providing that the CK_AK clock is present and se-

lected, indicated by CKAF_ST being set. The crys-

tal oscillator will be stopped automatically on en-

tering WFI if the WFI_CKSEL bit has been set. It

should be noted that selecting a non-existent

CK_AF clock source is impossible, since such a

selection requires that the auxiliary clock source

be actually present and selected. In no event can

a non-existent clock source be selected inadvert-

ently.

It is up to the user program to switch back to a fast-

er clock on the occurrence of an interrupt, taking

care to respect the oscillator and PLL stabilisation

delays, as appropriate.

It should be noted that any of the low power modes

may also be selected explicitly by the user pro-

gram even when not in Wait for Interrupt mode, by

setting the appropriate bits.

7.3.5 Interrupt Generation

System clock selection modifies the CLKCTL and

CLK_FLAG registers.

The clock control unit generates an external inter-

rupt request when CK_AF and CLOCK2/16 are

selected or deselected as system clock source, as

well as when the system clock restarts after a

hardware stop (when the STOP MODE feature is

available on the specific device). This interrupt can

be masked by resetting the INT_SEL bit in the

CLKCTL register. Note that this is the only case in

the ST9 where an interrupt is generated with a

high to low transition.

Table 21. Summary of Operating Modes using main Crystal Controlled Oscillator

MODE

INTCLK

CPUCLK

DIV2

PRS0-2

CSU_CKSEL

MX0-1

DX2-0

LPOWFI

XT_DIV16

PLL x BY 14

XTAL/2

x (14/D)

INTCLK/N

N-1

1 0

D-1

PLL x BY 10

XTAL/2

x (10/D)

INTCLK/N

N-1

0 0

D-1

PLL x BY 8

XTAL/2

x (8/D)

INTCLK/N

N-1

1 1

D-1

PLL x BY 6

XTAL/2

x (6/D)

INTCLK/N

N-1

0 1

D-1

SLOW 1

XTAL/2

INTCLK/N

N-1

111

SLOW 2

XTAL/32

INTCLK/N

N-1

WAIT FOR

INTERRUPT

If LPOWFI=0, no changes occur on INTCLK ,but CPUCLK is stopped anyway.

LOW POWER

WAIT FOR

INTERRUPT

XTAL/32

STOP

RESET

XTAL/2

INTCLK

111

EXAMPLE

XTAL=4.4 MHz

2.2*10/2

= 11MHz

11MHz

001

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