ST92F120JR9T datasheet(119/320 Pages) STMICROELECTRONICS

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ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)

EXTERNAL MEMORY SIGNALS (Cont’d)

Whenever it is sampled low, the System Clock is

stretched and the external memory signals (AS,

DS, DS2, RW, P0 and P1) are released in high-im-

pedance. The external memory interface pins are

driven again by the ST9 as soon as BREQ is sam-

pled high.

BACK (Alternate Function Output, Active low) indi-

cates that the ST9 has relinquished control of the

memory bus in response to a bus request. BREQ

is driven low when the external memory interface

signals are released in high-impedance.

At MCU reset, the bus request function is disabled.

To enable it, configure the I/O port pins assigned

to BREQ and BACK as Alternate Function and set

the BRQEN bit in the MODER register.

8.2.6 PORT 0

If Port 0 (Input/Output, Push-Pull/Open-Drain/

Weak Pull-up) is used as a bit programmable par-

allel I/O port, it has the same features as a regular

port. When set as an Alternate Function, it is used

as the External Memory interface: it outputs the

multiplexed Address 8 LSB: A[7:0] /Data bus

D[7:0].

8.2.7 PORT 1

If Port 1 (Input/Output, Push-Pull/Open-Drain/

Weak Pull-up) is used as a bit programmable par-

allel I/O port, it has the same features as a regular

port. When set as an Alternate Function, it is used

as the external memory interface to provide the 8

MSB of the address A[15:8].

The behavior of the Port 0 and 1 pins is affected by

the BSZ and ETO bits in the EMR1 register. Refer

to the Register description.

8.2.8 WAIT: External Memory Wait

WAIT (Alternate Function Input, Active low) indi-

cates to the ST9 that the external memory requires

more time to complete the memory access cycle. If

bit EWEN (EIVR) is set, the WAIT signal is sam-

pled with the rising edge of the processor internal

clock during phase T1 or T2 of every memory cy-

cle. If the signal was sampled active, one more in-

ternal clock cycle is added to the memory cycle.

On the rising edge of the added internal clock cy-

cle, WAIT is sampled again to continue or finish

the memory cycle stretching. Note that if WAIT is

sampled active during phase T1 then AS is

stretched, while if WAIT is sampled active during

phase T2 then DS is stretched. WAIT is enabled

via software as the Alternate Function input of the

associated I/O port bit (refer to specific ST9 ver-

sion to identify the specific port and pin). Under

Reset status, the associated bit of the port is set to

the bidirectional weak pull-up mode. Refer to Fig-

ure 60.

Figure 61. Application Example

RAM

64 Kbytes

A0-A15

A15-A8

ST9+

Q0-Q7

D1-D8

Q1-Q8

A0-A7/D0-D7

LATCH

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