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ST92F120JR9T 数据表(PDF) 139 Page - STMicroelectronics |
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ST92F120JR9T 数据表(HTML) 139 Page - STMicroelectronics |
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139 / 320 page ![]() 139/320 STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 10.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bit 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE REGISTER (STL) R241 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bit 7:0 = ST.[7:0]: Counter Low Byte. Writing to the STH and STL registers allows the user to enter the Standard Timer constant, while reading it provides the counter’s current value. Thus it is possible to read the counter on-the-fly. STANDARD TIMER PRESCALER REGISTER (STP) R242 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bit 7:0 = STP.[7:0]: Prescaler. The Prescaler value for the Standard Timer is pro- grammed into this register. When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256 STANDARD TIMER CONTROL REGISTER (STC) R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h) Bit 7 = ST-SP: Start-Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting Bit 6 = S-C: Single-Continuous Mode Select. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bit 5:4 = INMD[1:2]: Input Mode Selection. These bits select the Input functions as shown in Section 10.2.2.2, when enabled by INEN. Bit 3 = INEN: Input Enable. This bit is set and cleared by software. If neither the STIN pin nor the CLOCK2 line are present, INEN must be 0. 0: Input section disabled 1: Input section enabled Bit 2 = INTS: Interrupt Selection. 0: Standard Timer interrupt enabled 1: Standard Timer interrupt is disabled and the ex- ternal interrupt pin is enabled. Bit 1:0 = OUTMD[1:2]: Output Mode Selection. These bits select the output functions as described in Section 10.2.2.4. 70 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8 70 ST.7 ST.6 ST.5 ST.4 ST.3 ST.2 ST.1 ST.0 70 STP.7 STP.6 STP.5 STP.4 STP.3 STP.2 STP.1 STP.0 70 ST- SP S-C INMD 1 INMD 2 INEN INTS OUTM D1 OUTM D2 INMD1 INMD2 Mode 00 Event Counter mode 01 Gated input mode 10 Triggerable mode 11 Retriggerable mode OUTMD1 OUTMD2 Mode 00 No output mode 01 Square wave output mode 1x PWM output mode 9 |
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