ST92F120JR9T datasheet(218/320 Pages) STMICROELECTRONICS

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SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.6.5 Interrupt Management

The interrupt of the Serial Peripheral Interface is

mapped on one of the eight External Interrupt

Channels of the microcontroller (refer to the “Inter-

rupts” chapter).

Each External Interrupt Channel has:

– A trigger control bit in the EITR register (R242 -

Page 0),

– A pending bit in the EIPR register (R243 -

Page0),

– A mask bit in the EIMR register (R244 - Page 0).

Program the interrupt priority level using the EI-

PLR register (R245 - Page 0). For a description of

these registers refer to the “Interrupts” and “DMA”

chapters.

To use the interrupt feature, perform the following

sequence:

– Set the priority level of the interrupt channel used

for the SPI (EIPRL register)

– Select the interrupt trigger edge as rising edge

(set the corresponding bit in the EITR register)

– Set the SPIS bit of the CR register to select the

peripheral interrupt source

– Set the SPIE bit of the CR register to enable the

peripheral to perform interrupt requests

– In the EIPR register, reset the pending bit of the

interrupt channel used by the SPI interrupt to

avoid any spurious interrupt requests being per-

formed when the mask bit is set

– Set the mask bit of the interrupt channel used to

enable the MCU to acknowledge the interrupt re-

quests of the peripheral.

Note: In the interrupt routine, reset the related

pending bit to avoid the interrupt request that was

just acknowledged being proposed again.

Then, after resetting the pending bit and before

the IRET instruction, check if the SPIF and MODF

interrupt flags in the SR register) are reset; other-

wise jump to the beginning of the routine. If, on re-

turn from an interrupt routine, the pending bit is re-

set while one of the interrupt flags is set, no inter-

rupt is performed on that channel until the flags are

set. A new interrupt request is performed only

when a flag is set with the other not set.

10.6.5.1 Register Map

Depending on the device, one or two Serial Pe-

ripheral interfaces can be present. The previous

table summarizes the position of the registers of

the two peripherals in the register map of the mi-

crocontroller.

Address

Page

Name

SPI0

R240 (F0h)

DR0

R241 (F1h)

CR0

R242 (F2h)

SR0

R243 (F3h)

PR0

SPI1

R248 (F8h)

DR1

R249 (F9h)

CR1

R250 (FAh)

SR1

R251 (FBh)

PR1

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