ST92F120JR9T datasheet(263/320 Pages) STMICROELECTRONICS

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J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.8.7 Register Description

The JBLPD peripheral uses 48 registers that are

mapped in a single page of the ST9 register file.

Twelve registers are mapped from R240 (F0h) to

R251 (FBh): these registers are usually used to

control the JBLPD. See Section 10.8.7.1 Un-

Stacked Registers for a detailed description of

these registers.

Thirty-six registers are mapped from R252 (FCh)

to R255 (FFh). This is obtained by creating 9 sub-

pages, each containing 4 registers, mapped in the

same register addresses; 4 bits (RSEL[3:0]) of a

sub-page. See Section 10.8.7.2 Stacked Regis-

ters section for a detailed description of these reg-

isters.

The ST9 Register File page used is 23 (17h).

NOTE: Bits marked as “Reserved” should be left at

their reset value to guarantee software compatibil-

ity with future versions of the JBLPD.

Figure 120. JBLPD Register Map

STATUS

CLKSEL

R240 (F0h)

R241 (F1h)

R242 (F2h)

R243 (F3h)

R244 (F4h)

R245 (F5h)

R246 (F6h)

R247 (F7h)

R248 (F8h)

R249 (F9h)

R250 (FAh)

R251 (FBh)

R252 (FCh)

R253 (FDh)

R254 (FEh)

R255 (FFh)

TXDATA

RXDATA

TXOP

CONTROL

PADDR

ERROR

IVR

PRLR

IMR

OPTIONS

CREG0

CREG1

CREG2

CREG3

RDAPR

RDCPR

TDAPR

TDCPR

FREG0

FREG31

FREG30

FREG29

FREG28

FREG1

FREG2

FREG3

FREG4

FREG5

FREG6

FREG7

FREG10

FREG11

FREG9

FREG8

FREG12

FREG13

FREG15

FREG14

FREG16

FREG17

FREG18

FREG19

FREG20

FREG21

FREG22

FREG23

FREG24

FREG25

FREG26

FREG27

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