ADE75 datasheet(136/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 136 of 148

I2C COMPATIBLE INTERFACE

The ADE75XX/ADE71XX supports a fully licensed* I2C

interface. The I2C interface is implemented as a full hardware

master.

SDATA is the data I/O pin, and SCLK is the serial clock. These

two pins are shared with the MOSI and SCLK pins of the on-

chip SPI interface. Therefore, the user can enable only one

interface or the other on these pins at any given time. The SCPS

bit in the CFG SFR selects which peripheral is active.

The two pins used for data transfer, SDA and SCL are

configured in a Wired-AND format that allows arbitration in a

multi-master system.

The transfer sequence of a I2C system consists of a master

device initiating a transfer by generating a START condition

while the bus is idle. The master transmits the address of the

slave device and the direction of the data transfer in the initial

address transfer. If the slave acknowledges then the data transfer

is initiated. This continues until the master issues a STOP

condition and the bus becomes idle.

SERIAL CLOCK GENERATION

The I2C master in the system generates the serial clock for a

transfer. The master channel can be configured to operate in

Fast mode (256 kHz) or Standard mode (32 kHz).

The bit-rate is defined in the I2CMODE SFR as follow :

]

[

SCLDIV

core

SCL

SLAVE ADDRESSES

The I2CADR SFR contains the slave device ID. The LSB of this

start the I2C communication.

I2C SFR REGISTER LIST

The I2C peripheral interface consists of five SFRs:

I2CMOD

I2CSTAT

I2CADR

SPI2CTx

SPI2CRx.

As the SPI and I2C serial interfaces share the same pins, I2CMOD, I2CADR, I2CSTAT, SPI2CTx and SPI2CRx SFRs are also shared with

SPIMOD1, SPIMOD2, SPISTAT, SPI2CTx and SPI2CRx SFRs respectively.

SFR Address

Name

R/W

Length

Default

Value

Description

0x9A

SPI2CTx

SPI Data out register

0x9B

SPI2CRx

SPI Data in register

0xE8

I2CMOD

R/W

SPI configuration register

0xE9

I2CADR

R/W

SPI configuration register

0xEA

I2CSTAT

R/W

SPI/I2C Interrupt Status register

Table 134: SPI SFR register list

Table 135. I2C Mode Register SFR (I2CMOD, 0xE8)

Bit

Location

Bit

Addr.

Bit

Name

Default

Value

Description

0xEF

I2CEN

I2C enable bit

When this bit is set to logic one, the I2C interface is enabled. A write to the

I2CADR SFR will start a communication

6-5

0xEE –

0xED

I2CR[1:0]

I2C SCLK frequency

[1:0]

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