ADE75 datasheet(138/148 Pages) AD

138 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 138 of 148

Figure 85 and Figure 86 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select

whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated

automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also generated automatically after

I2CRCT[4:0] bytes have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a STOP

at the end of the read or write operation, the master will generate a START condition and continue with the next communication.

STOP BY

MASTER

SCL

SDA

START BY

MASTER

ACK BY

SLAVE

ACK BY

MASTER

FRAME 2

DATA BYTE 1 FROM SLAVE

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

NACK BY

MASTER

FRAME N+1

DATA BYTE N FROM SLAVE

Figure 85: I2C Read operation

SCL

SDA

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

FRAME 2

DATA BYTE 1 FROM MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

STOP BY

MASTER

R/W

Figure 86: I2C Write operation

I2C RECEIVE AND TRANSMIT FIFOS

The I2C peripheral has a four byte receive FIFO and a four byte

transmit FIFO. The buffers reduce the overhead associated with

using the I2C peripheral. Figure 87 shows the operation of the

I2C receive and transmit FIFOs.

The TX FIFO can be loaded with four bytes to be transmitted to

the slave at the beginning of a write operation. When the

transmit FIFO is empty, the I2C transmit interrupt flag will be

set and the PC will vector to the I2C interrupt vector if this

interrupt is enabled. If a new byte is not loaded into the TX

FIFO before it is needed in the transmit shift register, the

communication will stop. An error such as not receiving an

acknowledge will also cause the communication to terminate. In

case of an error during a write operation, the TX FIFO will be

flushed.

The RX FIFO allows four bytes to be read in from the slave

before the MCU has to read the data. A receive interrupt can be

generated after each byte is received or when the RX FIFO is

full. If the peripheral is reading from a slave address, the

communication will stop once the number of received bytes

equals the number set in the I2CRCT[4:0] bits. An error such as

not receiving an acknowledge will also cause the

communication to terminate.

I2CTX

TXDATA3

TXDATA2

TXDATA1

TRANSMIT SHIFT REGISTER

4 Byte FIFO

MOV I2CTX, TXDATA1

MOV I2CTX, TXDATA2

MOV I2CTX, TXDATA3

Code to fill TX FIFO:

I2CTX

TXDATA3

TXDATA2

TXDATA1

TRANSMIT SHIFT REGISTER

MOV I2CTX, TXDATA1

MOV I2CTX, TXDATA2

MOV I2CTX, TXDATA3

MOV I2CTX, TXDATA4

Code to fill TX FIFO:

I2CRX

RXDATA1

RXDATA2

RXDATA3

RXDATA4

RECEIVE SHIFT REGISTER

4 Byte FIFO

MOV A, I2CRX

; Result: A=RXDATA1

MOV A, I2CRX

; Result: A=RXDATA2

MOV A, I2CRX

; Result: A=RXDATA3

MOV A, I2CRX

; Result: A=RXDATA4

Code to read RX FIFO:

TXDATA4

Figure 87: I2C FIFO operation

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ADE75 数据表(PDF) 138 Page - Analog Devices

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