R8CSLASH2G datasheet(134/344 Pages) RENESAS

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R8C/2G Group

13. Interrupts

Rev.1.00

Apr 04, 2008

Page 114 of 318

REJ09B0387-0100

Figure 13.4

INTiIC Register (i=0, 1, 2, 4)

INTi Interrupt Control Register (i=0, 1, 2, 4)(2)

Symbol

Address

After Reset

INT2IC

0055h

XX00X000b

INT1IC

0059h

XX00X000b

INT0IC

005Dh

XX00X000b

INT4IC

005Eh

XX00X000b

Bit Symbol

Bit Name

Function

NOTES:

Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.

Refer to 13.5.5 Changing Interrupt Control Register Contents.

If the INTiPL bit in registers INTEN and INTEN2 are set to 1 (both edges), set the POL bit to 0 (selects falling edge).

The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 13.5.4 Changing Interrupt

Sources.

b7 b6 b5 b4 b3 b2 b1 b0

ILVL0

Interrupt priority level select bits

b2 b1 b0

0 0 0 : Level 0 (interrupt disable)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

Interrupt request bit

0 : Requests no interrupt

1 : Requests interrupt

RW(1)

POL

Polarity sw itch bit(4)

0 : Selects falling edge

1 : Selects rising edge(3)

—

(b5)

Reserved bit

Set to 0.

—

(b7-b6)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Only 0 can be w ritten to the IR bit. (Do not w rite 1.)

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