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R8C/2G 数据表(PDF) 137 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 137 Page - Renesas Technology Corp |
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137 / 344 page ![]() R8C/2G Group 13. Interrupts Rev.1.00 Apr 04, 2008 Page 117 of 318 REJ09B0387-0100 13.1.6.5 Interrupt Response Time Figure 13.6 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt response time includes the period between interrupt request generation and the completion of execution of the instruction (refer to (a) in Figure 13.6) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in Figure 13.6). Figure 13.6 Interrupt Response Time 13.1.6.6 IPL Change when Interrupt Request is Acknowledged When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 13.5 is set in the IPL. Table 13.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged. NOTE: 1. When non-maskable interrupts is selected. Table 13.5 IPL Value When Software or Special Interrupt Is Acknowledged Interrupt Source Value Set in IPL Watchdog timer, voltage monitor 1, voltage monitor 2, comparator 1(1), comparator 2(1), address break 7 Software, address match, single-step Not changed Interrupt request is generated. Interrupt request is acknowledged. Instruction Interrupt sequence Instruction in interrupt routine Time (a) 20 cycles (b) Interrupt response time (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (no wait and when the register is set as the divisor) (b) 21 cycles for address match and single-step interrupts. |
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