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R8C/2G 数据表(PDF) 141 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 141 Page - Renesas Technology Corp |
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141 / 344 page ![]() R8C/2G Group 13. Interrupts Rev.1.00 Apr 04, 2008 Page 121 of 318 REJ09B0387-0100 13.2 INT Interrupt 13.2.1 INTi Interrupt (i = 0, 1, 2, 4) The INTi interrupt is generated by an INTi input. Table 13.6 lists the Pin Configuration of INT Interrupt. When using the INTi interrupt, the INTiEN bit in registers INTEN and INTEN2 are set to 1 (enable). The edge polarity is selected using the INTiPL bit in registers INTEN and INTEN2, and the POL bit in the INTiIC register. Inputs can be passed through a digital filter with three different sampling clocks. Figure 13.11 shows the INTEN Register. Figure 13.12 shows the INTF Register. Figure 13.13 shows the INTEN2 Register. Figure 13.14 shows the INTF2 Register. NOTE: 1. The INT1 pin is selected by the INT1SEL bit in the PMR register and the TIOSEL bit in the TRAIOC register. Refer to 8. I/O Ports for details. Figure 13.11 INTEN Register Table 13.6 Pin Configuration of INT Interrupt Pin name Input/Output Function INT0 (P4_5) Input INT0 interrupt input, Timer RB external trigger input INT1 (P1_5, P1_7, or P3_6)(1) Input INT1 interrupt input INT2 (P3_2) Input INT2 interrupt input INT4 (P0_6) Input INT4 interrupt input External Input Enable Register Symbol Address After Reset INTEN 00F9h 00h Bit Symbol Bit Name Function RW INT0 _____ input enable bit INT0 _____ input polarity select bit(1, 2) INT1 _____ input enable bit INT1 _____ input polarity select bit(1, 2) INT2 _____ input enable bit INT2 _____ input polarity select bit(1, 2) NOTES: 1. 2. 0 — (b7-b6) b3 b2 b1 b0 b7 b6 b5 b4 0 RW INT0EN RW INT1PL 0 : One edge 1 : Both edges RW INT2PL When setting the INTiPL bit (i = 0, 1, 2) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling edge). The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 13.5.4 Changing Interrupt Sources. 0 : Disable 1 : Enable 0 : One edge 1 : Both edges Set to 0. RW INT0PL RW INT1EN 0 : Disable 1 : Enable Reserved bits RW INT2EN RW 0 : One edge 1 : Both edges 0 : Disable 1 : Enable |
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