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R8C/2G 数据表(PDF) 142 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 142 Page - Renesas Technology Corp |
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142 / 344 page  R8C/2G Group 13. Interrupts Rev.1.00 Apr 04, 2008 Page 122 of 318 REJ09B0387-0100 Figure 13.12 INTF Register Figure 13.13 INTEN2 Register INT _____ Input Filter Select Register Symbol Address After Reset INTF 00FAh 00h Bit Symbol Bit Name Function RW INT0 _____ input filter select bits INT1 _____ input filter select bits INT2 _____ input filter select bits RW 0 — (b7-b6) INT2F1 0 b1 b0 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW INT0F1 RW RW INT2F0 RW INT1F0 b3 b2 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW INT1F1 Set to 0. b5 b4 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW b7 b6 b5 b4 b3 b2 b1 Reserved bits INT0F0 b0 External Input Enable Register 2 Symbol Address After Reset INTEN2 02FDh 00h Bit Symbol Bit Name Function RW INT4 _____ input enable bit INT4 _____ input polarity select bit(1, 2) NOTES: 1. 2. — (b7-b2) b3 b2 b1 b0 b7 b6 b5 b4 — INT4EN When setting the INT4PL bit to 1 (both edges), set the POL bit in the INT4IC register to 0 (selects falling edge). The IR bit in the INT4IC register may be set to 1 (requests interrupt) w hen the INT4PL bit is rew ritten. Refer to 13.5.4 Changing Interrupt Sources. 0 : Disable 1 : Enable 0 : One edge 1 : Both edges RW INT4PL RW Nothing is assigned. If necessary, set to 0. When read, the content is undefined. |
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