H8SSLASH2225 datasheet(339/1071 Pages) RENESAS

339 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 253 of 982

REJ09B0054-0500

Figure 8.15 illustrates operation in block transfer mode when MARA is designated as a block area.

Address T

Address B

Transfer

Address T

Address B

1st block

2nd block

Nth block

Block area

Consecutive transfer

of M bytes or words

is performed in

response to one

request

Legend:

Address

Where :

= L

A + SAIDE

( 1)SAID (2DTSZ (N

1))

= L

B + DAIDE

( 1)DAID (2DTSZ (M N

1))

= Value set in MARA

= Value set in MARB

= Value set in ETCRB

= Value set in ETCRAH and ETCRAL

Figure 8.15 Operation in Block Transfer Mode (BLKDIR = 1)

ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a

single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.

ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register

for which a block designation has been given by the BLKDIR bit in DMACRA is restored in

accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.

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