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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2225 数据表(PDF) 340 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 340 Page - Renesas Technology Corp |
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340 / 1071 page  Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 254 of 982 REJ09B0054-0500 ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 8.16 shows the operation flow in block transfer mode. Acquire bus ETCRAL = ETCRAL 1 Transfer request? ETCRAL = H'00 Release bus BLKDIR = 0 ETCRAL = ETCRAH ETCRB = ETCRB 1 ETCRB = H'0000 Start (DTE = DTME = 1) Read address specified by MARA MARA = MARA + SAIDE ( 1)SAID 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE ( 1)DAID 2DTSZ MARB = MARB DAIDE ( 1)DAID 2DTSZ ETCRAH MARA = MARA SAIDE ( 1)SAID 2DTSZ ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 8.16 Operation Flow in Block Transfer Mode |
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