H8SSLASH2225 datasheet(375/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 289 of 982

REJ09B0054-0500

9.3

Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of

RXI0, for example, is the RDRF flag of SCI_0. As there are a number of activation sources, the

activation source flag is not cleared with the last byte (or word) transfer. Take appropriate

measures at each interrupt as shown in table 9.1, Activation source and DTCER clearance.

Table 9.1

Activation Source and DTCER Clearance

Activation

Source

When the DISEL Bit is 0 and the

Specified Number of Transfers Have

Not Ended

When the DISEL Bit is 1,or when the

Specified Number of Transfers Have

Ended

Software

activation

• The SWDTE bit is cleared to 0

• The SWDTE bit remains set to 1

• An interrupt is issued to the CPU

Interrupt

activation

• The corresponding DTCER bit

remains set to 1

• The activation source flag is cleared

to 0

• The corresponding DTCER bit is

cleared to 0

• The activation source flag remains set

to 1

• A request is issued to the CPU for the

activation source interrupt

When an interrupt has been designated a DTC activation source, the existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC operates in accordance with the default priorities.

Figure 9.2 shows a block diagram of activation source control. For details, see section 5, Interrupt

Controller.

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