H8SSLASH2225 datasheet(376/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 290 of 982

REJ09B0054-0500

CPU

DTC

DTCER

Source flag cleared

On-chip

peripheral

module

IRQ interrupt

Interrupt

request

Clear

controller

Clear request

Interrupt controller

Interrupt mask

Select

DTVECR

Figure 9.2 Block Diagram of DTC Activation Source Control

9.4

Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).

Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,

MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register

information.

In the case of chain transfer, register information should be located in consecutive areas as shown

in figure 9.3, and the register information start address should be located at the vector address

corresponding to the interrupt source. Figure 9.4 shows the correspondence between DTC vector

address and register information. The DTC reads the start address of the register information from

the vector address set for each activation source, and then reads the register information from that

start address.

When the DTC is activated by software, the vector address is obtained from: H'0400 +

(DTVECR[6:0]

× 2). For example, if DTVECR is H'10, the vector address is H'0420.

The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte

unit being used in both cases. These two bytes specify the lower bits of the register information

start address.

Note: * Normal mode cannot be used in this LSI.

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