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H8S/2225 数据表(PDF) 387 Page - Renesas Technology Corp

部件名 H8S/2225
功能描述  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2225 数据表(HTML) 387 Page - Renesas Technology Corp

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Section 9 Data Transfer Controller (DTC)
Rev. 5.00 Aug 08, 2006 page 301 of 982
REJ09B0054-0500
9.5.7
Number of DTC Execution States
Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of
states required for each execution status.
Table 9.6
DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 9.7
Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
Internal I/O
Registers
External Devices
Bus width
32
16
8
16
8
8
16
16
Access states
1
1
2
2
2
3
2
3
Vector read SI
1

4
6 + 2 m 2
3 + m
Execution
Status
Register information
read/write SJ
1

Byte data read SK
1
1
2
2
2
3 + m
2
3 + m
Word data read SK
1
1
4
2
4
6 + 2 m 2
3 + m
Byte data write SL
1
1
2
2
2
3 + m
2
3 + m
Word data write SL
1
1
4
2
4
6 + 2 m 2
3 + m
Internal operation SM 1
Legend:
m: The number of wait states for accessing external devices.
The number of execution states is calculated from using the formula below. Note that
Σ is the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM



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