H8SSLASH2225 datasheet(389/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 303 of 982

REJ09B0054-0500

9.7

Examples of Use of the DTC

9.7.1

Normal Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.

1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address

(DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit

can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).

Set the SCI RDR address in SAR, the start address of the RAM area where the data will be

received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.

2. Set the start address of the register information at the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the

reception complete (RXI) interrupt. Since the generation of a receive error during the SCI

reception operation will disable subsequent reception, the CPU should be enabled to accept

receive error interrupts.

5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag

in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is

transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.

The RDRF flag is automatically cleared to 0.

6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is

held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The

interrupt handling routine will perform wrap-up processing.

9.7.2

Software Activation

An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means

of software activation. The transfer source address is H'1000 and the destination address is

H'2000. The vector number is H'60, so the vector address is H'04C0.

1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination

address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =

0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE

= 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in

DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.

2. Set the start address of the register information at the DTC vector address (H'04C0).

3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer

activated by software.

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