H8SSLASH2225 datasheet(388/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 302 of 982

REJ09B0054-0500

For example, when the DTC vector address table is located in the on-chip ROM, normal mode is

set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for

the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

9.6

Procedures for Using DTC

9.6.1

Activation by Interrupt

The procedure for using the DTC with interrupt activation is as follows:

1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.

2. Set the start address of the register information in the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC

is activated when an interrupt used as an activation source is generated.

5. After one data transfer has been completed, or after the specified number of data transfers

have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the

DTC is to continue transferring data, set the DTCE bit to 1.

9.6.2

Activation by Software

The procedure for using the DTC with software activation is as follows:

1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.

2. Set the start address of the register information in the DTC vector address.

3. Check that the SWDTE bit is 0.

4. Write 1 to SWDTE bit and the vector number to DTVECR.

5. Check the vector number written to DTVECR.

6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not

requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the

SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers

have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.

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