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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2225 数据表(PDF) 722 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 722 Page - Renesas Technology Corp |
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722 / 1071 page  Section 16 I 2C Bus Interface (IIC) (Option) Rev. 5.00 Aug 08, 2006 page 636 of 982 REJ09B0054-0500 SCL in SCL out SDA in SDA out (Slave 1) SCL in SCL out SDA in SDA out (Slave 2) SCL in SCL out SDA in SDA out (Master) This LSI SCL SDA VDD VCC SCL SDA Figure 16.2 I2C Bus Interface Connections (Example: This LSI as Master) 16.2 Input/Output Pins Table 16.1 shows the pin configuration for the I2C bus interface. Table 16.1 Pin Configuration Name Abbreviation* I/O Function Serial clock SCL0 I/O IIC_0 serial clock input/output Serial data SDA0 I/O IIC_0 serial data input/output Serial clock SCL1 I/O IIC_1 serial clock input/output Serial data SDA1 I/O IIC_1 serial data input/output Note: * Pin names SCL and SDA are used in the text for all channels, omitting the channel designation. 16.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible addresses differ depending on the ICE bit in ICCR. SAR and SARX are accessed when ICE is 0, and ICMR and ICDR are accessed when |
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