H8SSLASH2225 datasheet(730/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 644 of 982

REJ09B0054-0500

16.3.6 I2C Bus Control Register (ICCR)

I2C bus control register (ICCR) consists of the control bits and interrupt request flags of I2C bus

interface.

Bit

Bit Name

Initial

Value

R/W

Description

7ICE

R/W

2C Bus Interface Enable

When this bit is set to 1, the I

2C bus interface module is

enabled to send/receive data and drive the bus since it is

connected to the SCL and SDA pins. ICMR and ICDR can be

accessed.

When this bit is cleared, the module is halted and separated

from the SCL and SDA pins. SAR and SARX can be

accessed.

6IEIC

R/W

2C Bus Interface Interrupt Enable

When this bit is 1, interrupts are enabled by IRIC.

MST

TRS

R/W

Master/Slave Select

Transmit/Receive Select

00: Slave receive mode

01: Slave transmit mode

10: Master receive mode

11: Master transmit mode

Both these bits will be cleared by hardware when they lose in

a bus contention in master mode of the I

2C bus format. In

slave receive mode, the R/

W bit in the first frame immediately

after the start automatically sets these bits in receive mode or

transmit mode by using hardware. The settings can be made

again for the bits that were set/cleared by hardware, by

reading these bits. When the TRS bit is intended to change

during a transfer, the bit will not be switched until the frame

transfer is completed, including acknowledgement.

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